I think about every single CPU unit have been designed to maximize computational power either in multi-task or to a 1-2 simultaneous process.
Now, with UNICODE and multi-level as layered approach, we can easily trash out about everything, and increase speed or data in transit, and the level of accessibility. (It's already in use if you think about VR or AR that use multi-level and layers) you can remove and keep only what is required for your task. Most phone now have 8-12-16 cpu core as 4 or 8 X2 with virtual allocation, and probably none of them, use a quarter of this power. Most apps are made for binary unit and so these type arent't made in order to multi-task.
With a new version of ARM, you could do a 2-1 as 64-128 and push this to 256 easy... The goal is to reduce energy consumption, improve latency and optimize singular or multi-task when necessary, and build an architectural style in prevision of quantum network & connectivity.
What I am thinking is that, at this stage, to redesign a new chip and a board, could be pretty easy and still affordable (probably not the first year but each subsequent) and from there, in theory we could simply trash those legacy or old chip since the price to manufacture those now and the material used, is cheaper than ever.
In short, current stack propose a 56 virtual mem allocation with 128
• 56-bit virtual addresses.
• 128-bit System registers.
• 128-bit atomic instructions.
So instead of going back and forth with only a slight % increase (even if lastly this was a huge step forward to copy NVIDIA architecture style as distributed cpu unit :BlobPain: ) I assume that each future unit shoud be build as modular and interoperable architecture with at least 4 layer and the layer ground zero as the fifth (without going deep in details)