Logic Design - Classes in SystemVerilog (part 2)

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Introduction

Hey it's a me again @drifter1!

Today we continue with the Logic Design series on SystemVerilog in order to cover more about Classes. This is part 2 and so I highly suggest checking out part 1 beforehand.

So, without further ado, let's dive straight into it!

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Classes (...)

Copying Objects

Last time we showed how multiple objects can point to the same instance:

className i1, i2;
i1 = new();     // object creation
i2 = i1;        // point to same instance

Copying an object can be done using the keyword new followed by the corresponding instance name.

className i3;
i3 = new i2;

But, be careful, as this approach (a "shallow" copy) doesn't take care of nested objects. For nested objects we have to make a "deeper" copy by writing a custom task, let's say copy(), and copying any necessary data over in that task.

class className;
    nestedObject no;
    task copy(ref className other);
        begin
        other = new this;
        other.no = new this.no;
        ...
        end
    endtask
endclass

Of course, this task is called on the to-be-copied object, and the target is put as a parameter!

className i4;
i1.copy(i4);

Inheritance

Being OOP, SystemVerilog also offers Inheritance, which is the concept of OOP that allows a class to extend another class. That way, properties and methods from the parent (or super) class can be called from the child (or sub) class.

Inheriting from a class is done by adding the extends keyword followed by the super class's name in the class declaration.

class className extends superClass;
    ...
endclass

Methods from the parent class can of course be overridden by adding a new definition for them in the sub class.

From within the inheriting class (not anywhere else!) its possible to access the parent class's original properties and methods using the super keyword. That way the methods of the class can call the original methods.

For example, a print() task could call the original print() together with new code.

task print()
    begin
        ...
        super.print();
        ...
    end
endtask

Polymorphism

SystemVerilog allows us to assign a subclass to the superclass's handler. This is known as Polymorphism.

For example:

parentClass pc;
subClass sc;

sc = new();

pc = sc;

Even though pc points to sc, the original (parent class) methods and not the overridden methods will be called instead!

Assigning the parent class's handler to the subclass's handler is not possible and will yield a compilation or runtime error.

sc = pc;    // not possible

Virtual Methods

Continuing on from the previous topic of Polymorphism, what if we want to invoke the child class method instead of the parent class method? Well, simply mark the corresponding methods as virtual, which basically states that different definitions can be given by any child class.

So, what the following code executes depends on if the example() method was marked as virtual in the parent class.

pc = sc;

pc.example();

• no keyword : superclass's example() method
• virtual keyword : subclass's example() method

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RESOURCES:

References

1. https://www.chipverify.com/systemverilog/systemverilog-tutorial
2. https://www.asic-world.com/systemverilog/tutorial.html

Images

1. https://www.flickr.com/photos/creative_stock/5227842611

Block diagrams and other visualizations were made using draw.io

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Previous articles of the series

Verilog

• Introduction → Basic Syntax, Data Types, Operators, Modules
• Combinational Logic → Assign Statement, Always Block, Control Blocks, Gate-Level Modeling and Primitives, User-Defined Primitives
• Combinational Logic Examples → One Circuit - Four Implementations, Encoder, Decoder, Multiplexer
• Sequential Logic → Procedural Blocks (Initial, Always), Blocking and Non-Blocking Assignments, Statement Groups
• Sequential Logic Examples → Flip Flops (DFF, TFF, JKFF, SRFF), N-bit Counter, Single-Port RAM
• Finite-State Machines → Finite-State Machine (FSM), FSM Types, State Encoding, Modeling FSMs in Verilog
• Finite-State Machine Examples → Moore FSM Example (1 and 2 always blocks), Mealy FSM Example (1, 2 and 3 always blocks)
• Testbenches and Simulation → Testbenches (DUT / UUT, Syntax, Test Cases), System Tasks, Simulation Tools
• Combinational Logic Testbench Example → Half Adder Implementation, Testbench and Simulation
• Sequential Logic Testbench Example → Sequence Detector FSM Implementation, Testbench and Simulation
• Functions and Tasks → Function and Task Syntax, Calling, Rules, Examples
• Module Parameters and Generate Block → Parameterized Module (Parameters, Instantiation and Overriding Parameters), Generate Blocks (For, If, Case)
• Compiler Directives → Summary of Verilog's Compiler Directives (Include, Macros, Timescale, Conditional Compilation, etc.)
• Switch Level Modeling → Transistors, Switch Primitives (NMOS, PMOS, CMOS, Bidirectional, Resistive), Signal Strengths

SystemVerilog

• From Verilog To SystemVerilog → Data Types, Arrays, Structures, Operators and Expressions
• Control Flow → Additional Procedural Blocks, Loops, Conditional Statements, Functions and Task Features
• Processes → Fork - Join in Verilog and SystemVerilog, Process Control (wait fork, disable fork)
• Events → Interprocess Communication, Events (Definition, Triggering, Waiting, Sequencing, Merging, as Arguments)
• Semaphores and Mailboxes → Semaphores (Creation, Methods), Mailboxes (Definition, Methods)
• Interfaces (part 1) → Interfaces (Definition, Port and Signal Lists, Instantiation), Modports
• Interfaces (part 2) → Parameters, Tasks and Functions (Importing, Exporting), Clocking Blocks (Input and Output Skews)
• Classes (part 1) → Classes (Definition, Constructor Function, Creating Objects, Accessing Class Members, Static and Constant Class Members, Arrays)

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Final words | Next up

And this is actually it for today's post!

Next time we will continue on with more on Classes...

See Ya!

Keep on drifting!